A Low-Power Continuous-Time Delta-Sigma ADC with Low Noise Low Voltage Supply Bandgap Reference Voltage and RC Time-Constant Calibration Technique for Biomedical Systems

• Main Authors: Guan-Shun Li, 李冠舜
• Other Authors: Muh-Tian Shiue
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/05293175008455705690

碩士 === 國立中央大學 === 電機工程學系 === 105 === With the increment of average age of people, various bio-medical wearable devices have been launched, especially for the elders. Therefore, how to reduce the power consumption and area to achieve the portability as well as the long battery life-time requirements are demands of this thesis. This thesis consists of three parts, the first part designs a continuous-time delta-sigma modulator (CTDSM) for bio-medical application to ease the requirements of hardware rather than discrete-time DSM using an OPA to achieve the second-order integration. Besides, the current-reusing technique is used to maintain flicker noise and thermal noise to lower level and to keep low power consumption. In the second part, a bandgap voltage reference (BGR) is introduced to meet low-noise and low supply voltage requirements. It can provide a stale voltage reference without the variation of temperature for feedback reference of DSM and other sub-circuits. Third, the drawback of a CTDSM is the dependence on the variation of environment temperature and process. Therefore, the RC Time-Constant Calibration method is proposed for detecting and compensating the variation of RC time-constant. Finally, by introducing a decimation, we integrate all sub-circuits to a complete continuous-time delta-sigma ADC. Designs in this thesis are fabricated in the UMC 0.18 μm 1P6M CMOS process. In order to pursue low-power consumption, the supply voltage is all set up as low as 1.2 V. First, the measurement of CTDSM achieves 78.42 dB SNDR, 12.73 bits ENOB, and power consumption 15.97 μW at 10 kHz signal bandwidth with X128 OSR, 0.6 Vp-p amplitude and chip area is 0.67mm*0.56mm, including PAD and seal-ring. Second, BGR generates a stable 0.6 V voltage reference which is tunable with flicker and thermal noise 0.496nV^2/(0.1~10 kHz) in the bandwidth for 17.3 μW. Finally, the simulation of the complete CT delta-sigma ADC achieves 81.31 dB SNDR, 13.21 bits ENOB, and power consumption 71.82 μW, including CTDSM, BGR, RC Time-Constant Calibration and buffers. The whole chip area is 1.74mm*1.11mm, including PAD and seal-ring.