| Summary: | 博士 === 國立交通大學 === 電子研究所 === 105 === In today’s nanometer technology, IC design and system design become more complex. There are thousands of nets and hundreds of components on a printed circuit board while package dimensions keep shrinking. Board-level routing issues are more critical than before and are unable to do them manually. The conditions and constraints of boardlevel routing are different from on-chip signal routing. Crosstalk, IR drop, impedance matching must be considered to satisfy board routing requirement. Besides, board routing uses non-orthogonal paths and prefers planar paths. As a result, board routing must take net shape and net length into consideration.
In addition to board design, analog design performance is also sensitive to layout. Early estimation of parasitic and layout dependent effect is essential to analog design
flow. Fast information exchange between schematic and layout design stages are desired instead of conventional one-pass flow. Design prototyping becomes a popular way to explore design performance. In design prototyping, multiple layout candidates are generated for early estimation of overall performance. However, these candidate layouts must be generated carefully such that it can demonstrate its own strength and weakness. Symmetry
constraint, topology matching, and length matching all affect circuit performance. Similar to board-level routing, the needs of special constraint routing in analog design flow is more important than ever.
In this dissertation, we introduce the conditions and constraints in board-level routing and analog routing. We review routing approaches that have been used to solve these special constraint routing tasks. Novel routing models and algorithms are presented. A two stage routing method for board-level area routing is proposed to arrange routing paths among board components while considering min-max length constraint. A sequence-based approach is proposed to consider multiple component escaping problem. A routing path extraction and preservation technique based on constrained Delaunay triangulation (CDT) is proposed, which makes fast layout prototyping flow work.
In chapter 2, we focus on board-level area routing problem. A sequence based planar path search algorithm is presented. The algorithm selects cross-free nets from given nets, calculates a planar routing order, and form the routing paths on board. An ILP-based net length adjustment is then used to refine routing paths to mitigate length constraints while maintaining net shapes. Combined with the planar path searching and length
adjustment, we propose a two stage routing approach to complete signal routing among board components while considering min-max length constraints. Experimental results show that the proposed approach uses routing resource effectively while min-max length constraints are satisfied.
In chapter 3, we discuss escape routing problem among multiple components. A sequence-based approach is presented to search planar routing solutions among multiple components. In the proposed approach, an escape order generation is first applied to generate a set of possible escape order candidates. A dynamic routing graph is designed for planar path finding among multiple components. By considering component positions,
the proposed method can avoid possible crossings among nets belonging to different busses or components. Area routing topologies are also provided through the proposed method. Experimental results show that the proposed approach can produce feasible escape routing solutions for multiple components.
In chapter 4, we introduce the path topology extraction and preservation problem for analog design prototyping and migration. A constrained Delaunay triangulation (CDT) based routing topology extraction and preservation technique is proposed. For a given layout,
the proposed method extracts routing topology and stored the extracted information
on a CDT-based graph data structure called crossing graph. The extracted information
can be reconstructed on a new placement. The path preservation technique is applied
on layout reusing in analog layout prototyping and migration. Based on the preservation
technique, a hierarchical layout prototyping/migration flow is presented. In the proposed flow, we generate placements using a slicing-based approach, and extract/reconstruct routing results using the proposed CDT preservation. The simulation results of the generated
layout candidates is comparable with manual layout. The proposed automatic flow allows designer to fast explore design performance in circuit development.
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