Low-Power Signal Conversion and Memory Circuits for Neural Signal Recording Microsystem

• Main Authors: Wu, Shang-Lin, 吳尚霖
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/nfx3tp

博士 === 國立交通大學 === 電子研究所 === 105 === Investigating and monitoring the human brain activity has attracted prominent attention for bio-medical applications. One of substantial challenges is to develop high-density microsystem for real-time recording. Low-Power signal acquisition and memory circuit are crucial in the devices for preventing the damage during monitoring. Furthermore, area-efficiency is also a concern for integrating and miniaturizing neural sensing microsystem. Therefore, area-power efficiency neural signal conversion and low-power memory circuit have been investigated for high-density neural sensing applications. Firstly, for neural acquisition, we present an energy-efficient low-noise 16-channel neural-signal acquisition IC. The 16-channel acquisition IC comprises 16 low-noise analog amplifier with pseudo-resistor and 4 area-power-efficient 11-bit hybrid analog-to-digital converters (ADC). In this design, differential difference amplifiers (DDAs) design is used for achieving low-noise and energy efficiency. Additionally, the modified pseudo resistor with symmetric resistance property is designed to remove high DC offset from input signal. Moreover, the 11-bit hybrid ADC is designed by combining a coarse-tuning 3-bit delay-line-based ADC and a fine-tuning 8-bit successive approximation register (SAR) ADC to reduce area and power consumption. And follow up the previous 16-CH design; an area-power-efficient 64-Channel (64-CH) acquisition IC is proposed for further enhancing spatiotemporal-resolution. This 64-CH acquisition circuitry is composed of 16 4-CH low-noise digitally-assisted chopper-stabilized DC-compensation neural amplifiers and 16 area-power-efficient hybrid ADCs. The proposed 4-CH neural amplifiers is designed by using four DDAs and one shared chopper-stabilized DC-compensation circuitry. Furthermore, a dual-voltage SAR ADC with a self-timed power-management unit (ST-PMU) is designed to reduce power consumption and mitigate leakage. Secondly, in order to store and process information, low-power sub/near threshold SRAM designs are also proposed, including the disturb-free symmetrical 10T subthreshold SRAM with tri-state bit-line and the mini-array based 6T SRAM with Vtrip-tracking write-assist. In 10T cell design, the disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity. The fully-symmetrical cell structure provides balanced performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. To maintain manufacturability, the array of mini-array based 6T cell SRAM is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable ultra-short local bit-line (LBL) of 4 bit length to improve variation tolerance and performance, and to reduce disturb. Moreover, the cell Vtrip-tracking write-assist (VTWA) design lowers the column cell supply to cell inverter trip voltage (Vtrip) to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected column.