| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 105 === This thesis investigates the impact of interlayer coupling on the stability and performance of monolithic 3D 7T SRAM cell composed of TFETs and MOSFETs operating at ultra-low voltage. We compare the 3D result with 2D counterparts, and compared hybrid case with pure MOSFET case. In addition, we investigate the impact of WFV and LER for monolithic 3D SRAMs considering interlayer coupling.
TCAD simulation result indicates that the planar (2D) 7T hybrid TFET-MOSFET SRAM cell exhibits equal leakage, better stability and performance compared with the conventional 2D 8T MOSFET SRAM at ultra-low voltage (VDD ≤ 0.3V). The interlayer coupling, where the front-gate of the bottom tier device alters the back gate bias of the upper tier device, and various stacking and layout arrangements are examined and exploited to improve the stability and performance of monolithic 3D SRAMs. An optimized 3D design is shown to exhibit the best WSNM and cell write performance improvement over the planar design. However, the hybrid case has better improvement than pure MOSFET case. Furthermore, 3D SRAM designs reduce cell area by 40%.
The impacts of work function variation (WFV) and line edge roughness (LER) on SRAM cell stability, leakage power and performance are investigated and compared. The results indicate that WFV and LER have different impacts on read disturb and Vwrite,0, which dominate SRAM stability and is determined by the distinct current drive of TFET and MOSFET. The performance is influenced by the different variations of gate capacitance (Cg) under WFV and LER.
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