Area-Power Efficiency Reconfigurable Multi-Queue Architecture for IoT Routers

碩士 === 國立交通大學 === 電子研究所 === 105 === In the era of big data and Internet of Things (IoT), sensors and mobile devices are ubiquitous. The great number and high diversity of sensor data make the whole system difficult to collect and store these data. A memory system with high bandwidth, flexible, recon...

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Bibliographic Details
Main Authors: Lin, Yu-Tao, 林于滔
Other Authors: Hwang, Wei
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/00830720044425860619
Description
Summary:碩士 === 國立交通大學 === 電子研究所 === 105 === In the era of big data and Internet of Things (IoT), sensors and mobile devices are ubiquitous. The great number and high diversity of sensor data make the whole system difficult to collect and store these data. A memory system with high bandwidth, flexible, reconfigurable, controllable low power storage is urgent needed for IoT routers. This paper presents a data allocation unit using reconfigurable multi-queue architecture for IoT applications. The proposed architecture consists of four parts: receiver interface, data allocation unit, link-based multi-queue FIFO and network interface. The implementation and simulation results show the proposed architecture achieves up to 31.3% performance improvement and 7.8% power reduction with 10.2% area overhead.