Investigation and Analysis of Ultra-Thin-Body Hetero-Channel III-V/Ge MOSFETs and Mono-/Few-Layer 2-D Transition-Metal-Dichalcogenide Based Logic Circuits and SRAM Cells

• Main Authors: Yu, Chang-Hung, 余昌鴻
• Other Authors: Su, Pin
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/87955385284377994089

博士 === 國立交通大學 === 電子研究所 === 105 === This dissertation provides an extensive assessment of the scalability of the exploratory ultra-thin-body (UTB) III-V/Ge hetero-channel MOSFETs and the performance/stability of 2-D transition-metal-dichalcogenide (TMD) based logic circuits and SRAM cells. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of the emerging TMD hetero-channel devices from the device/circuit point of view. Through our analysis, the impacts of quantum confinement, backgate biasing, and device variability are investigated to offer insights for future low-voltage device/circuit designs. A new intrinsic mechanism “built-in effective body-bias (VBS,eff) effect” related to the vertical backgate coupling in UTB hetero-channel GeOI and III-V-OI MOSFETs is reported and quantified to be responsible for the anomalous electrostatic integrity (EI) behaviors which violate the expectation of permittivity. For hetero-channel n-MOSFETs, this effect results from the conduction band offset (composed of discrepancies in electron affinity and the effective density-of-states of conduction band) between the high-mobility channel and conventional Si channel. For hetero-channel p-MOSFETs, this effect stems from the valence band offset (which mainly comes from the discrepancies in channel band-gap for Ge pFETs). From the perspective of electrostatic integrity, the built-in effective body-bias effect is shown to be a detrimental effect (whose impact can be comparable to that of permittivity) for most III-V-OI nFETs and the GeOI pFET, and thus the device electrostatics can be worse than what permittivity predicts. In addition, it is shown that the In0.53Ga0.47As-OI nFET and GeOI pFET may possess worse threshold-voltage (VT) variability than the GeOI nFET counterparts due to the aggravated EI by the built-in forward VBS,eff effect. The L-, EOT-, Tch-, TBOX-dependences of the impact of built-in VBS,eff on device electrostatics are also examined and discussed. This intrinsic effect has to be considered when one-to-one comparisons among various UTB hetero-channel MOSFETs regarding the electrostatic integrity are made. The quantum confinement effect becomes critical as channel-thickness keeps scaling down, and its impacts on the device electrostatic integrity and the intrinsic VT variability are theoretically investigated through an analytical solution of Schrödinger equation corroborated with TCAD numerical simulation. Besides, the backgate-bias modulated electrostatic integrity (including drain-induced-barrier-lowering (DIBL), subthreshold swing, and VT roll-off) and VT variability considering qunatum confinement are also analyzed. Our study indicates that albeit the carrier density distribution of the hetero-channel device can be far from the frontgate interface due to the high channel permittivity and the built-in forward body-bias effect, the quantum-confinement effect can move the carrier centroid toward the frontgate, and therefore the device EI such as DIBL and subthreshold swing can be improved and becomes comparable to the Si device. Moreover, the quantum confinement effect lessens the backgate-bias dependences of device electrostatic integrity and the intrinsic VT variability to process and temperature variations for UTB III-V/Ge hetero-channel devices. In other words, the backgate-bias dependence of the within-die VT variation can be suppressed by the quantum confinement effect as the backgate bias is used for power-performance optimization or global variability compensation. Since III-V, Ge and Si channels exhibit different degree of quantum confinement due to different quantization effective mass, the impact of quantum confinement has to be considered when one-to-one comparisons among the hetero-channel devices regarding electrostatic and intrinsic variability are made. Our study may provide insights for multi-VT device/circuit designs using advanced UTB technologies. 2-D layered TMD materials have emerged as promising channel materials for future ultimately-scaled CMOS devices due to the atomic-scale body thickness. We extensively evaluate the performance of logic circuits and the stability/performance of SRAM cells using mono-layer and bi-layer TMD devices based on ITRS 2028 (5.9nm) technology node. For the static CMOS logic family, albeit the bi-layer TMD devices possess higher mobility than the mono-layer counterpart, the mono-layer and bi-layer static CMOS logic circuits may show comparable delay time. On the other hand, for the pass-transistor logic family, the bi-layer pass-transistor logic circuits may exhibit much slower delay time that the mono-layer ones counterparts, particularly for those using single nMOS pass-gate transistors instead of transmission gate as signal propagation switches (e.g., the programmable routing switches in FPGAs). In the SRAM evaluations, the mono-layer MoS2-n/WSe2-p SRAM, with superior device electrostatics, is shown to exhibit larger read static noise margin (RSNM), smaller write static noise margin (WSNM), and comparable read/write performance compared with the bi-layer counterparts. Besides the nominal evaluations, the impacts of intrinsic random variations on the cell stability of 6T/8T TMD based SRAM cells for super-threshold and near-/sub-threshold operations are also conducted. Our study indicates that, for 6T SRAM, due to severe metal gate work function variation (WFV) stemming from the tiny gate area, the mono-layer SRAMs may offer sufficient immunity under super-threshold operation, while both the mono-layer/bi-layer near-/sub-threshold SRAMs exhibit unacceptable RSNM variability in spite of the excellent electrostatics of mono-layer TMD devices. Besides, high source/drain series resistance (RSD) as a major concern of TMDs may degrade the / ratios for mono-layer and bi-layer super-threshold SRAMs, whereas it should be less of an issue for near-/sub-threshold SRAMs for ultra-low power internet-of-things (IoT) applications. The standard 8T SRAM cell with the capability of elimination of read disturb may be utilized to improve the noise margin for variation tolerance. Our results show that the RSNM variations due to WFV of both mono-layer and bi-layer near-/sub-threshold SRAMs can be significantly improved by using 8T cell structure, and thus the 6 RSNM yield requirement can be met. Based on our evaluation, due to the excellent device electrostatics stemming from its single atomic layer, the mono-layer TMD devices are favored for low-power logic and SRAM applications; while the bi-layer devices, with higher carrier mobility, are more suitable for relaxed channel length and high-performance logic and SRAM applications. Our research in TMD based logic circuits and SRAM cells is also extended from planar technology to monolithic 3-D integration. The performance of 3-D logic circuits and performance/stability of 3-D 6T SRAM cells using mono- and few-layer TMD devices are comprehensively evaluated and benchmarked against the planar technology. With the possibility of adopting mono-layer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, our study indicates that using the tri-layer devices for nFET- or pFET-tiers may substantially degrade the performance of logic circuits (compared with the planar technology and other 3-D combinations) due to worse subthreshold swing and DIBL even though their mobilities are much higher. For monolithic 3-D 6T SRAMs, stacking the mono-layer pFET-tier over the bi-layer nFET-tier can provide superior stability and read/write performance for 6T super-threshold SRAM cells compared with the planar technology. However, the optimum 3-D configuration for 6T near-/sub-threshold SRAM cell appears to be the mono-layer pFET-tier over the mono-layer nFET-tier. Besides the 6T cell structure, Monolithic 3-D 8T SRAM cells are also investigated under near-/sub-threshold operation. The mono-layer nFET-tier over the bi-layer pFET-tier configuration has been shown to be the optimum 3-D 8T near-/sub-threshold cell design.