An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
碩士 === 國立交通大學 === 電子研究所 === 105 === Packing and Placement are two crucial stages for FPGA implement. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/aqx79a |