| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 105 === An ADPLL with spread spectrum circuit, fractional-N circuit, spur reduction circuit, and higher order loop filter is presented. By modulating the output frequency with the triangular profile generator, the simulated EMI reduction can be 30dB. The reference spurs which may mix the signals from adjacent channels can be dealt with by using the spur reduction circuit. When the channel spacing is small, the fractional-N circuit can be utilized for its higher frequency resolution. In the presence of input noise, the ADPLL can select the whole loop as a higher order by turning on the IIR filter to attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to main tone at higher-order ADPLL, will be analyzed in this thesis.
The chip has been designed and implemented in TSMC 40nm GP 1P9M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the LDO are using standard cell, therefore, it can be easily migrated from one technology to another. The total area of the ADPLL core is 0.0257mm2. The simulated RMS jitter from a 5.376GHz output frequency is 0.05% UI. The total power consumption is 5.36mW at 5.376GHz output frequency and 84MHz reference clock.
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