Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09342547578752013230 |