Architectural Optimization for a Quad-Core Java Processor

• Main Authors: Chen, Cheng-Yang, 陳政揚
• Other Authors: Tsai, Chun-Jen
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/rv2rvr

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === This thesis is developed based on a quad-core Java Application IP (JAIP-MP). We change the bus protocol from PLB to AXI4 and use two different controllers to solve the coherence problems, which appeared after the protocol modification. The first controller, cache data coherence controller, uses broadcasting mechanism to manage the coherence of the cache data between cores. The second controller is called the heap manager coherence controller, which manages the coherence and atomic of the heap allocation pointer while the heap was allocated by the JAIP cores or the RISC core. For the single core, we develop three methods to speed up accessing to the cache. The first method is to build a cache-like lookup table for field accessing. The second method is to reduce the cache stalled cycles while the cache is writing data back to the heap through the bus. The third method is to improve the mutex lock mechanism since cache accessing and the context switching will compete with each other, resulting a signal conflict while running a multithreading program. With these three methods, we gain much better efficacy in both single-core and quad-core JAIP. Finally, we add the component that completely supports 64-bit long type ALU and relative instructions to the JAIP in order to enhance the support of the Java language speculation in the JAIP.