Power Evaluation Platform for Low Voltage IoT Architecture and Its Usage in Energy-Efficient Design

• Main Authors: Rizal, Tanjung, 陳維勝
• Other Authors: Chen, Tien-Fu
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/40141324328686413053

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === Energy efficiency has become very important requirement in designing IoT (internet of things) devices, especially devices that are powered by battery. Many methods have been used to improve the energy efficiency, such as asymmetric core architecture, DVFS or various power saving modes. Asymmetric cores have been implemented in many architecture to improve the energy efficiency in various range of tasks, but there needs a power evaluation to show a certain task will be energy efficient in certain core. Furthermore, many microcontrollers (MCU) used in low-voltage IoT devices includes various power modes to improve the energy efficiency and energy saving. Those power modes are a trade-off between energy saving and system-wakeup overhead. Existing power evaluation tools do not take the wakeup overhead into account which is very important in evaluating the overall energy efficiency or energy saving. In this thesis, we propose a power evaluation platform for low-voltage IoT architecture. This power platform consisted of core power model, memory power model, and sensors/peripherals power model. We build the power library for each of those components and use them for the architectural-level exploration in low-voltage IoT application that support DVFS, mode transition overhead, and full IoT scenario. We show the power/energy analysis of asymmetric core architecture in an IoT scenario and the trade-off between energy saving and transition overhead in different sleep modes.