Design and Implementation of 94 GHz CMOS Down-Conversion Mixer Using Current-Bleeding and Modified Derivative Superposition (DS) Techniques

• Main Authors: LIAO JIN-YOU, 廖晉佑
• Other Authors: LIN,YO-SHENG
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/qk7n9j

碩士 === 國立暨南國際大學 === 電機工程學系 === 105 === This thesis mainly utilizes standard TSMC 90 nm CMOS process technology to implement down-conversion mixers and positive feedback low noise amplifier for W-band. The thesis is composed of four sections: In the first section, the high gain CMOS down-conversion mixer which is implemented in meteorological observation radar in W-band. This mixer is consisted of a double balanced mixer, a current bleeding technology and modified derivative superposition (DS) techniques. A current bleeding schematic is composed of a pair of PMOS and it will inject current into tranconductance stage which can transform voltage to current. In addition to raise the conversion gain, this method can reuse current to decrease power consumption. And using modified derivative superposition (DS) techniques will get better linearity. A 94 GHz Marchand balun for converting the single LO input signal to differential signal, and another Marchand balun for converting the single RF input signal to differential signal. Generally speaking, this work can demonstrate a high gain, great linearity and low power consumption mixer. In the second section, a positive feedback low noise amplifier working in W-band is implemented. This low noise amplifier is 2nd stage. There is an architecture using stable positive feedback applies in 1st stage. According to the formulation of feedback gain, it shows that the positive feedback architecture will increase gain effectively and gain can be controlled by capacitance. Although the stability will be influenced, it can be adjusted the inductance value to maintain high stability. The 2nd stage uses cascade structure. The purpose of this structure is to increase isolation. Because of using 2nd stage only, the power consumption and chip area will be decreased both. In the third section, a 180 GHz CMOS down-conversion mixer is implemented. This mixer adpots 40nm process. The architecture of this work adopts a pair of Gilbert cell, PMOS cross-coupling and NMOS current injection architecture. And there is an Inter-stage inductor which will resonant parasitic capacitance to reduce the noise figure. In addition, there is a 188 GHz Marchand balun for converting the single LO input signal to differential signal, and another Marchand balun for converting the single RF input signal to differential signal. Generally speaking, this work can demonstrate a high gain, great linearity and low power consumption mixer. The last part is conclusion, it shows that all performance of these chips.