| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 105 === In this thesis, an “Ultra-High Step-Down Ratio Converter with Extended Duty Cycle and Low Output Current Ripple” is proposed. Due to the change of the server and distribution infrastructure, eliminating 12 V intermediate conversion stage, a high step-down voltage converter is required to convert 48 V bus voltage to the operating voltage of microprocessor as low as 1 V. Proposed converter can achieve the required conversion ratio with an adequate duty cycle compared to the other topologies. Furthermore, this converter has an inherent interleaved structure, which can share the currents, reduce the conduction loss. Besides, interleaved structure can reduce the output current ripple and thus shrink the size of output filter. On the other hand, four out of five switches will resonate with leakage inductor and therefore can be turned on with ZVS, thus enhancing the conversion efficiency. In this thesis, operating principles, steady-state analysis, and component parameter designs are presented. Finally, a hardware prototype with 48 V input voltage, 1 V output voltage, and 30 W output power is implemented to verify the feasibility of the proposed converter.
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