| Summary: | 碩士 === 國立成功大學 === 資訊工程學系 === 105 === Median filter is widely used in digital signal processing and image processing to filter out the noises in signals and images. The hardware implementation of median filter plays an important role in some real-time applications.
A low-power architecture of one-dimensional median filter is proposed in this dissertation. Two techniques are implemented in the proposed architecture to reduce power consumption. First of all, a low-power FIFO is proposed for dynamic power reducing. The low-power FIFO reduces the power consumption by minimizing the switching activities. To further reduce power consumption, the clock gating technique is also implemented in the circuit. A high proportion of registers will preserve its original value at each clock cycle, especially for large window size median filters. Thus, turning off these registers can also reduce a lot of power consumption.
The architectures in this dissertation were implemented by the Verilog HDL, and synthesized by Synopsys Design Compiler with the TSMC 90nm standard cell library. The experimental results show that the proposed architecture can reduce power consumption as well as achieve nearly the same operating speed and area cost, compared with the state-of-art techniques.
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