A High-Speed Encoding Module for Gray and Binary Codes Transformation

• Main Authors: Hao-Ping Chan, 詹皓評
• Other Authors: Yu-Cherng Hung
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/7y837e

碩士 === 國立勤益科技大學 === 電子工程系 === 105 === Bell Labs researcher Frank Gray proposed Gray code in 1940, so named Gray code in succeeding study. The code characteristics of the adjacent value is only one bit transition in difference. When the code value changes, Gray code unlike traditional binary code will not vary more than two bits in simultaneously. The property of Gray code implies is with less transient codes occurred due to various time delay of digital data paths in circuit realization. A modular 8-bit high-speed Gray code and binary code encoding circuit is proposed in this study, by using the concepts of carry select adder (CSA) and add one circuit to improve operating speed. The circuit is designed by using TSMC CMOS 90-nm process. The length of eight bit circuit is one module circuit. Three modules is in cascaded to realize 24 bit Gray-to-Binary transformation and vice vesa. Simulation results show that the improved circuit works successfully in 1 GHz under 24 bits length. In contrast to conventional design, the maximum operation speed of the traditional desogn is only capable of 500 MHz.