| Summary: | 碩士 === 國立勤益科技大學 === 電子工程系 === 105 === In this thesis, a decoding circuit for multiple codes with on-line self-checking capability is proposed. Three commonly codes including FM0, Manchester, and Miller decoder are successfully integrated in a single chip. These codes are useful for radio frequency identification (RFID) applications. In addition, in order to enhance the reliability, the technique of two-rail code is adopted to achieve a self-checking function. The circuit is realized by TSMC 0.18-μm 1P6M CMOS technology. By using HSPICE simulation, the maximum operation frequency of 100 MHz is achieved. The power consumption of the decoding circuit is 2.006mW in average.
Simulations results show that the circuit is capable of on-line detect the single-stack fault. However, due to the technique limitation of two-rail code, the error of two faults occurred simultaneously is not detectable by this circuit. The chip layout of the proposed circuit is finished. In the near future, the functions of the experimental chip will be measured.
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