A Novel Design of Quadrature Voltage Control Oscillator

• Main Authors: Min-Yao Lo, 羅閔耀
• Other Authors: Shao-Hui Shieh
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/9y29z8

碩士 === 國立勤益科技大學 === 電子工程系 === 105 === A simple oscillator design approach is proposed in this thesis. By using this approach, two Quadrature Voltage Control Oscillators (QVCO) are proposed, and to compare with four previous works. Based on TSMC CMOS 1P6M 0.18um standard process technology with supply voltage 1.8V, Spectre-RF and HSPICE are used to perform simulation on four previous QVCOs and two proposed QVCOs. Proposed Type-Ⅰand Type-Ⅱ QVCO schemes have significantly decreased phase noise (Pnoise), which are -128.51dBc/Hz and -133.01dBc/Hz at 1 MHz offset frequency, respectively. Type-Ⅰhas the lowest power dissipation to be 3.54mW, Type-Ⅱ has the lowest phase noise to be -133.01 and the best FoM (Figure of Merit) to be -183.21dBc/Hz.