| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 105 === In recent years, the measurement of velocities and distances of objects become gradually draw people’s attentions. There are various methods but some of them will be affected by weather or light, thereby influencing the accuracy. On the other hand, radar does not have this problem, so this thesis adopts radar to extract distance and velocity. One type of radars uses the continuous wave radar transmitting a fixed frequency electromagnetic wave. Although the speed can be calculated using the Doppler principle, the distance can not be obtained. Therefore, this thesis selects the Frequency-Modulated Continuous-Wave (FMCW) radar which transmits a continuous wave radar with the frequencies varying over time. It can simultaneously detect the distance and velocity of the object. However, this type of radars needs to change the frequency rapidly, so the VCO non-linearity is the issue to be solved.
During study of the VCO non-linearity, several digital calibration methods were invetigated but most of them are cumbersome and/or require a given reference target. Besides, they all employ software to do calibration and correction, which makes the calibration/correction process slow. For the demand of fast correction and scanning images, designing hardware to speed up calculation is desired. Without modification of the exiting algorithms to design hardware, it will make the hardware too complicated and long computation time. Therefore, we modify the correction algorithm without placing the reference target and simplifying the calibration process to reduce hardware complexity and computation time. The object distance accuracy after correction is improved by 80% to 95% for 10%~16% linearity errors.
As for the hardware implementation, this thesis proposes a digital calibration/correction processing circuit, the key functional blocks are FFT/IFFT, "High-Order Ambiguity Function (HAF)" and "Time Resampling". The FFT/IFFT circuit was designed by using Radix-2 algorithm. The HAF hardware architecture used multiple sets of FFT, Find Max Peak Position and complex-number multipliers. In order to reduce the hardware complexity, only one set was designed and worked in turns with the other small circuits to control the calculation flow. Finally, implementation of digital calibration/correction process was performed using Virtex7 XCVX330T of Xilinx platform for verification. The APR tool of ISE Design Suite 14.5 version was used with the synthesis clock rate of 115.567 MHz, and APR clock rate of 107.388 MHz.
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