| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系 === 105 === Abstract
According to Moore’s Law, the manufacture of semi-conduction is going to face the bottleneck. The Fabrications as TSMC, UMC and Memory Fabrications as Micron, NAYA, are pursuing for low cost and high output now. In wafer manufacture process, testing field is always the 1st considered stage to be cost down. In Taiwan, there are many professional OSAT (testing houses) such as ASET, SPIL and ADT, KYEC which are in service for wafer and IC testing. Therefore, consider to cost down effectively is a critical topic.
As we enter the deep submicron age, it is getting harder for traditional test equipment to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers has become a wide concern. To solve this issue, we propose a “wireless testing technical of probe card”.
The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. Wireless testing of preliminary feasibility study has been done for a period of time. In this paper, present some economics models and simulating results of probe card. The result shows that wireless testing will be much more cost-effective than traditional physical contact.
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