Retinex by FPGA Implementation

碩士 === 輔仁大學 === 電機工程學系碩士班 === 105 === Bad images induced by insufficient light often lead to unclear object contour, color cast phenomenon, and wrong object recognition. Retinex is one of well-known image enhancement algorithms. However it cannot achieve real-time processing because of its high comp...

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Bibliographic Details
Main Authors: WU, LIU-MING, 吳律明
Other Authors: WANG, YUAN-KAI
Format: Others
Language:zh-TW
Published: 2017
Online Access:http://ndltd.ncl.edu.tw/handle/466g59
Description
Summary:碩士 === 輔仁大學 === 電機工程學系碩士班 === 105 === Bad images induced by insufficient light often lead to unclear object contour, color cast phenomenon, and wrong object recognition. Retinex is one of well-known image enhancement algorithms. However it cannot achieve real-time processing because of its high computational complexity. We propose a 2D-1D filter to reduce the computational complexity of Retinex, and implement it using FPGA pipeline architecture, so that it can achieve real-time image processing. In our experiment, we use a Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation Kit, and 24-bit color images with the resolution of 1280x720. In terms of execution speed, our design is 34.76 times faster than the original Retinex algorithm executing on PC. Our method can achieve real-time performance with 58.217 FPS.