| Summary: | 碩士 === 輔仁大學 === 資訊工程學系碩士班 === 105 === With the wide application of computer graphics, many handheld devices in market have embedded graphics acceleration systems. Moreover, there is a quick development of applying 3D graphics on multimedia and game systems. The study of this thesis is motivated by the research of using FPGA’s for versatile applications like accelerating voice recognition and Image Processing in computer graphics. Due to the fact that large datasets and elapsed CPU time for 3D graphics computation, this thesis addresses on FPGA’s hardware acceleration and batch processing of datasets to reduce the computing time. To implement our proposed hardware acceleration of 3D graphics, Altera DE2-115 board was adopted as our hardware design and experimental platform. Firstly, we use Altera’s SOPC (System-On-a-Programmable-Chip) builder to configure the 3D graphics hardware system. Secondly, we design the digital circuit which implements geometry techniques and lifting algorithm usually used in computer graphics.
During the research process of our study, we encounter several hard issues. In the beginning, DE2-35 board was used for developing our system and then we found that it cannot fulfill the design requirements since the deficiency of gates count in FPGA chip on DE2-35 board. Therefore, we transform the hardware platform to DE2-115 board to solve this problem. After that, we found the sample codes provided by Altera cannot work with DE2-115 board. It took much time to revise these codes to make it running correctly in our system. Furthermore, we made a big adjustment to the sample codes of IP acceleration to fulfill the design requirement. By the preliminary experimental result, it showed that we cannot improve the system performance because the main system overload is from the large dataset of light source. Based on this observation, we fixed the problem and optimized our design to increase the overall system performance.
Our proposed FPGA platform can accelerate the light processing of 3D graphics pipeline (Rendering Pipeline). Firstly, we reference the source codes of 3D software which covers the associated geometry mathematics. After porting our system into the Nios system, instruction set and customized IP are used to improve the system performance. We test our implemented system under DE2-115 developing environment. Compared with the spot light software version computation of 3D graphics system, our proposed hardware version can improve the system performance by 290%. Using accelerating instruction set can improve the system performance by 47%. The overall system performance can be improved about 64%.
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