| Summary: | 碩士 === 逢甲大學 === 電子工程學系 === 105 === This thesis studies the electrical characteristics of Junctionless FET (JLFET) with raised source/drain. The channel material of JLFET device is polysilicon. The device structure is TiN/Al2O3/Poly-Si. This work investigates the device electrical characteristics, including threshold voltage (Vth), subthreshold swing (S.S.), drain induced barrier lowering (DIBL) and device driving current on/off ratio (Ion/Ioff). Additionally, the raised source/drain JLFET with localized anti-channel doping, spacer capping, and the performance comparison of long and short channel device are also studied.
For the results of the spacer-capped JLFET with and without the raised source/drain structure, the device with raised source/drain can increase the drain current and obviously reduce the Ioff, resulting the better S.S. value. Presumably, the raised source/drain structure reduced the series resistance in the source/drain region, leading to the driving current improvement. For the results of the raised source/drain JLFET with and without spacer capping, the n-type JLFET device with spacer capping reveals better performance of S.S and current on/off ratio (Ion/Ioff). But for the p-type JLFET device with long channel reveals the opposite result. Thus, the spacer capping degrades the device characteristics of p-type JLFET. Presumably, the over-etching process of spacer formation leads to the thinner channel and the surface damage, resulted in the lower driving current. In the comparison of the raised source/drain JLFET with and without localized anti-channel doping, n-type JLFETs with BF2 ions anti-channel doping reveal better performance of S.S. and Ioff. But for p-type JLFET with long channel, the arsenic ions anti-channel doping present the worse device performance. The lower driving current is caused by the anti-channel ion doping and the channel resistance increase.
Finally, as channel length reducing gradually, the JLFET with anti-channel doping presents the smallest short channel effect. In addition, the raised source/drain JLFETs with spacer capping show the better S.S. value and current on/off ratio for both short and long channel devices.
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