Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes

碩士 === 逢甲大學 === 材料科學與工程學系 === 105 === Nowadays, the scales of integrated circuit along with advances in semiconductor technology and continuing to miniaturization, so it’s imperative to enhance the internal density and chip performance of the components. Recently, the development of the semiconduct...

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Main Authors: WANG, WEI-CHENG, 王韋程
Other Authors: CHEN, GIIN-SHAN
Format: Others
Language:zh-TW
Published: 2017
Online Access:http://ndltd.ncl.edu.tw/handle/60353811510876511892
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spelling ndltd-TW-105FCU001590122017-08-11T04:22:14Z http://ndltd.ncl.edu.tw/handle/60353811510876511892 Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes 孔隙介電層上之全程無電鍍鈷合金包覆銅導線研製 WANG, WEI-CHENG 王韋程 碩士 逢甲大學 材料科學與工程學系 105 Nowadays, the scales of integrated circuit along with advances in semiconductor technology and continuing to miniaturization, so it’s imperative to enhance the internal density and chip performance of the components. Recently, the development of the semiconductor industry is focused on reducing the width of metal wires and increasing stacking layers. In order to avoid the problem of RC delay caused by the reducing width and increasing length of the wires, it’s great concern and research on using high conductivity copper wires and low k dielectric layer materials. In this study, we use nanoporous dielectric ultra low k (ULK) materials, named Black DiamondTM III (BD III) to fabricate copper wires by all-electroless plating. We use the techniques, such as: (1) Surface hydroxylation modified. (2) Self-Assembled Monolayer (SAM) deposition. (3) SAM surface functionalization and deprotonation. (4) Catalytic seed fixed. (5) Electroless deposition of Co-alloy barrier layers. (6) Electroless deposition of Cu wires and (7) Co-alloy capping layers deposition by electroless plating on dielectric layers. First, the leakage currents and dielectric constants of the BD III surface hydroxylated by SC-1 solution were measured with the dielectric properties (J-E, C-V), and using attenuated total reflection Fourier transform infrared spectroscopy (ATR-FTIR) to evaluate the surface bonding changes and hydroxylation effects. According to the results, short-time (10 seconds) modification by SC-1 solution not only achieves hydroxylation effects on BD III, but also causes non-serious damage. After hydroxylation treatment, octadecyltrichlorosilane self-assembled monolayer (OTS-SAM) is deposited on the BD III surface, and the surface is highly hydrophobic. A slight and short-seconds plasma treatment cause the surface becomes hydrophilic. Then, deprotonation by SC-1 solution makes the surface presents negative potential and attracts metal ions, and the metal ions are reduced to the catalytic seed particles fixed on the OTS-SAM for the subsequent electroless Co-alloy barrier layers deposition. Electroless plating Cu wires can easily deposited on Co-alloy surface, according to Co-alloy self-catalytic effect. In order to increase the reliability of Cu wires, this study adopts electroless plating homogeneous metal as capping layers, that is, Cu wires are capped by Co-alloy capping layers. Adding the strong reducing agent into Co-alloy plating solution, Co-alloy capping layers can be precipitated on the Cu wires to achieve a completely capped effect. Finally, a constant current stress is applied to the Cu wires which are uncapped and capped by Co-alloy, to measure the difference in reliability. It is confirmed by the measurement results that Co-alloy capping layers can prolong the electromigration life of Cu and greatly increase the reliability of Cu wires. CHEN, GIIN-SHAN 陳錦山 2017 學位論文 ; thesis 123 zh-TW
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language zh-TW
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description 碩士 === 逢甲大學 === 材料科學與工程學系 === 105 === Nowadays, the scales of integrated circuit along with advances in semiconductor technology and continuing to miniaturization, so it’s imperative to enhance the internal density and chip performance of the components. Recently, the development of the semiconductor industry is focused on reducing the width of metal wires and increasing stacking layers. In order to avoid the problem of RC delay caused by the reducing width and increasing length of the wires, it’s great concern and research on using high conductivity copper wires and low k dielectric layer materials. In this study, we use nanoporous dielectric ultra low k (ULK) materials, named Black DiamondTM III (BD III) to fabricate copper wires by all-electroless plating. We use the techniques, such as: (1) Surface hydroxylation modified. (2) Self-Assembled Monolayer (SAM) deposition. (3) SAM surface functionalization and deprotonation. (4) Catalytic seed fixed. (5) Electroless deposition of Co-alloy barrier layers. (6) Electroless deposition of Cu wires and (7) Co-alloy capping layers deposition by electroless plating on dielectric layers. First, the leakage currents and dielectric constants of the BD III surface hydroxylated by SC-1 solution were measured with the dielectric properties (J-E, C-V), and using attenuated total reflection Fourier transform infrared spectroscopy (ATR-FTIR) to evaluate the surface bonding changes and hydroxylation effects. According to the results, short-time (10 seconds) modification by SC-1 solution not only achieves hydroxylation effects on BD III, but also causes non-serious damage. After hydroxylation treatment, octadecyltrichlorosilane self-assembled monolayer (OTS-SAM) is deposited on the BD III surface, and the surface is highly hydrophobic. A slight and short-seconds plasma treatment cause the surface becomes hydrophilic. Then, deprotonation by SC-1 solution makes the surface presents negative potential and attracts metal ions, and the metal ions are reduced to the catalytic seed particles fixed on the OTS-SAM for the subsequent electroless Co-alloy barrier layers deposition. Electroless plating Cu wires can easily deposited on Co-alloy surface, according to Co-alloy self-catalytic effect. In order to increase the reliability of Cu wires, this study adopts electroless plating homogeneous metal as capping layers, that is, Cu wires are capped by Co-alloy capping layers. Adding the strong reducing agent into Co-alloy plating solution, Co-alloy capping layers can be precipitated on the Cu wires to achieve a completely capped effect. Finally, a constant current stress is applied to the Cu wires which are uncapped and capped by Co-alloy, to measure the difference in reliability. It is confirmed by the measurement results that Co-alloy capping layers can prolong the electromigration life of Cu and greatly increase the reliability of Cu wires.
author2 CHEN, GIIN-SHAN
author_facet CHEN, GIIN-SHAN
WANG, WEI-CHENG
王韋程
author WANG, WEI-CHENG
王韋程
spellingShingle WANG, WEI-CHENG
王韋程
Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
author_sort WANG, WEI-CHENG
title Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
title_short Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
title_full Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
title_fullStr Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
title_full_unstemmed Investigation of Co-Alloy Encapsulated Cu Wires Fabricated on Porous Dielectric Layers by Using All-Electroless Plating Processes
title_sort investigation of co-alloy encapsulated cu wires fabricated on porous dielectric layers by using all-electroless plating processes
publishDate 2017
url http://ndltd.ncl.edu.tw/handle/60353811510876511892
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