The accompanied effects of process-oriented and temperature cycling loadings on the warpage of thin-type 3D-ICs packaging structure and the creep behavior of microjoints

• Main Authors: Hou-Chun Liu, 柳厚均
• Other Authors: Chang-Chun Lee
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/45262807612088466725

碩士 === 中原大學 === 機械工程研究所 === 105 === Owing to the fact that requirements of the lifestyle for electronis devices has been shifted to a stage physically small and thin, a high density of chips is designed to meet the foregoing demand under the limited space. Although the technology of 2D-ICs packaging technology has been maturely developed, it has encountered a bottleneck which stops it from immediate progress: Therefore, it is inevitable that the 3D-ICs packaging technology becomes the major goal of technological developments in the future. Among them, through silicon via is one of the critical techniques. Because of the complexity in the design of 3D-ICs, the interaction among packaging components is expected to affect the reliability. Consequently, this research presents two 3D-ICs packaging with ultra-thin chip stacking to examine their mechanical reliability TSV structure and SnAg microjoints under only the thermal cycling loads and the accompanied effect of process-oriented and temperature cycling loads. Several concerned parameters, such as the thickness of chip, the TSV pitch , and TSV radius, for the foregoing two packaging structures are discussed by finite element analysis when the underfill materials with different Young''s modulus are taken into account. The simulated results show that when the double-layered chip stacking packaging structure is applied by the thermal cycling period, a better fatigue life of SnAg microjoint can be obtained under the situation of either the thinner chip, the longer TSV pitch, or the smaller TSV radius. On the other hand, a similar result would be acquired for a single-layered chip stacking packaging structure under the accompanied effects of process-oriented and temperature cycling loading. Finally, through the analytic assistance of full factoral design, the double-layered chip stacking packaging is performed parameterically investigations for its geometrics. The results show that when the thickness of each layer chip is 10 μm, the TSV pitch is 230 μm, and TSV radius is 5 μm, the SnAg solder microjoint would achieve its best fatigue life time under the considered designed range.