VLSI architecture of a cost-efficient reconfigurable colour interpolation image processor design

• Main Authors: Wen-Xuan Zhao, 趙文瑄
• Other Authors: Shih-Lun Chen
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22105CYCU5428051%22.&searchmode=basic

碩士 === 中原大學 === 電子工程研究所 === 105 === This thesis presents a low-complexity algorithm for interpolating colour compensation. The proposed colour interpolation algorithm was implemented by a low-complexity and real-time image processing integrated circuit design. The proposed design is based on a low-cost and high-quality algorithm. It consists of two filters which are Laplacian filter and spatial sharpening filter. The Laplacian filter and spatial sharpening filter reduce the lack of boundary information and enhance the details of the fuzzy regions to increase the interpolated image quality. All multiple operations in the procedure of the proposed low-complexity algorithm are multiplied by the power of two. This method can reduce the cost of hardware using shifter to replace the multipliers. The image processor contains a two-line-buffer memory to avoid missing pixel. This study improves the main operation of the reference [1] with a circuit hardware sharing technology to increase the logical utility rate. First, the functions of the proposed design were verified by field programmable gate array. Second, the proposed design was synthesized by a Design Compiler toolSecond, this paper synthesizes this design with Design Compiler. Finally, the proposed design used the IC Compiler tool to auto place and route for chip implementationFinally, this paper uses IC Compiler to auto place and route to implement chip. The VLSI architecture of this design is 2.58K gate counts and its core area is 32.2K μm2 synthesized by a TSMC 0.18 μm CMOS processThe VLSI architectures in this design is 2.58K gate counts and its core area is 32.2K um2 synthesized by a 0.18 um CMOS process. It works on the frequency of 200MHz and consumes the power of 3.38mW. Compared with the previous references, this design decreases the gate counts about 11% and maintains high image qualityand maintains image quality in the peak signal to noise ratio.