| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 105 === The purpose of this paper is to improve the power consumption and design area of traditional 6-bit R-2R ladder-based current-steering Digital to Analog Converter. Use folding technology to reduce almost half of the R-2R resistors, and the same unit resistance value’s area also reduce to achieve the purpose of reducing the area. Because of using folding technology, the number of current control switches is also reduced from 48 unit current to 28 unit current; it almost reduces nearly 60%, and achieves the purpose of reducing the power consumption. This paper designs DAC specifications by using rigorous formulas, and explores its static and dynamic characteristics. The power consumption simulation results is 7.25
mW(no Buffer). The ENOB of 5.79 bits, when the input frequency of 50MHz, SFDR of48.46dB. Design platform is TSMC 0.18 μm 1P6M CMOS process.
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