A Design of Global Maximum Power Point Tracking Systems for Small Photovoltaic Panels Using Voltage Sweep

• Main Authors: SUNG, CHI-YING, 宋奇穎
• Other Authors: TSAI, TSUNG-HENG
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/sxnffs

碩士 === 國立中正大學 === 電機工程研究所 === 105 === This thesis completes a design of global maximum power point tracking systems for small photovoltaic panels using voltage sweep. Although light energy is ubiquitous and can generate large amounts of energy in the surrounding environment, however, when the partially shaded conditions occurs on solar panels, the best working point is drifted so that the P-V electrical curve presents multiple maxima, resulting in reduced energy extraction. Therefore, a global maximum power point tracking system is required to track the optimum operating point voltage corresponding to multiple maxima to improve the efficiency of energy extraction. In this thesis, the algorithm uses voltage sweep method. The use of power transistor and opamp to form a negative feedback loop, as long as a given reference voltage, Vpv can be stable to reference voltage, and then through the step to increase the voltage can get information of Vpv, current of power transistor is the information of Ipv, have both the information and use the circuit to achieve the algorithm, can get the maximum power point voltage. In order to avoid sampling capacitor leakage effect, the analog information will be converted to digital code to operate, and through the D-type flip-flop to store digital code. Finally, the digital-to-analog converter converts the digital code of maximum power point into analog voltage. The time to track to the global maximum power point is about 10ms, the system standby time is 10s, and the tracking peak efficiency of the global maximum power point voltage is 99.38%. Finally, parallelly connected solar panels with different specifications were constructed in the experiment. VOC are 2.5-V and 4-V, respectively, and the dimensions are 60×65 mm2 and 60×110 mm2, respectively. The chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M CMOS mixed-signal polycide process. The package of chip is 48 S/B and the die area of the chip is 2.1×1.8 mm2.