Variation-Resilient Adaptive Voltage Scaling Control Loop Design

• Main Authors: CHANG, YU-SIAN, 張裕銑
• Other Authors: LIN, TAY-JYI
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/yckr6a

碩士 === 國立中正大學 === 資訊工程研究所 === 105 === Traditionally, to estimate one of AVS control parameters of AVS results takes large simulation time, pre-error AVS system have been proposed to simplify the procedure of estimate AVS result, which just simulated delay distributions at different voltage for once with Markov chain to estimate all set of AVS control parameters of AVS result. In this paper, we evaluate pre-error AVS system in 90nm CMOS, using delay distributions of 100,000 patterns and 20mV step voltage and Markov chain to estimate the AVS result which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 34.86%, but the error of RMSE of voltage scatter with AVS in 90nm CMOS is 2.78% while increasing the patterns to 10,000,000 patterns, the reason of this difference is the tail information of delay distribution is not enough (i.e. limit precision). We proposed using delay distributions of 1,000 patterns with Interpolate Gaussian mathematic model to replace delay distributions of 100,000 patterns to estimate AVS results which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 5.68%. We also analysis the sensitivity of AVS control parameters (N, nlimit↓, nlimit↑) which the result is N> nlimit↓> nlimit↑, therefore, fixed n_lb=1, n_ub=N*2% and adjust N to get the difference error rate from control parameters, and evaluate the adjust method in 90nm CMOS to get the error rate from 10-2 to 10-5.