Recompression algorithm on video coding system application development and hardware architecture design

• Main Authors: Yi-Guo Chen, 陳益國
• Other Authors: Yu-Hsuan Lee
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/50286958279391751406

碩士 === 元智大學 === 電機工程學系 === 104 === Video coding systems induces tremendous memory bandwidth requirement on external memory. This bandwidth is directly proportional to display resolution and frame rate. The aspiration of high-end visual quality drives display resolution and frame rate upgraded to a certain level. With this trend, the design bottleneck on the memory bandwidth drastically arises. In this paper, Multi-Direction Lossless Recompression (MDLR) and Parallel and Hierarchical Lossless Recompression (PHLR) are proposed to eliminate the above design bottleneck. MDLR includes two core techniques: (1) Multi-Directional Prediction and (2) Direction-Adaptive Golomb-Rice code. And PFLR includes two core techniques: (1) Parallel and Hierarchical Prediction and (2) The Binary Code. The Parallel and Hierarchical Prediction can obtain an efficient residual. Then, the Binary Code converts it into an efficient codeword. The experiment result reveals that MDLR can save the memory bandwidth of the video coding system as high as 42% on average without any loss on visual quality. This work is realized into a silicon chip with the technology of TSMC 0.18um CMOS process. Its encoding capability can reach Full-HD (1920 x 1080)@60fps. The chip power consumption is 10.31mW @125MHZ. Core area and chip area are 0.29x0.29mm^2, respectively. And the PHLR can reduce video transmission capacity as high as 56% on average without any loss on visual quality. This work is realized into a silicon chip with the technology of TSMC 0.18um CMOS process. Its encoding capability can reach Full-HD (1920 x 1080)@38fps. The chip power consumption is 12.37mW @100MHZ. Chip’s core area is 0.76 x 0.76mm^2, respectively.