Thermal-Aware Kernel and Memory Mapping Architecture Design for Three-Dimensional Multi-Mode Channel Decoding Systems
碩士 === 元智大學 === 電機工程學系 === 104 === In modern wireless communication standards, such as LTE and WiMAX, the turbo code and low-density parity-check (LDPC) code [2] are applied because of the excellent ability in forward error correction (FEC). To support multiple standards in a chip, many dual-mode...
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| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12817917289651318897 |
| Summary: | 碩士 === 元智大學 === 電機工程學系 === 104 === In modern wireless communication standards, such as LTE and WiMAX, the turbo code and low-density parity-check (LDPC) code [2] are applied because of the excellent ability in forward error correction (FEC). To support multiple standards in a chip, many dual-mode forward error correction (DFEC) designs have been proposed to support turbo and LDPC decoding. In this work, the thermal-managed three-dimensional dual-mode forward error correction (3D DFEC) architecture is proposed. In 3D DFEC, the reconfigurable block-based SRAM architecture can support the memory requirement in different active DFEC kernels and the decoding modes. The thermal issue can be solved by the proposed thermal-aware mappings.
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