An SAT Approach to Routing of 15nmStandard Cells
碩士 === 元智大學 === 資訊工程學系 === 104 === In spite of rapid progress in semiconductor process technology, the variation in the feature sizes of generated patterns continues to create problems due to prolonging use of 193nm lithography. To scale down the feature sizes continually, more complex design rules...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/uv3x2n |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 104 === In spite of rapid progress in semiconductor process technology, the variation in the feature sizes of generated patterns continues to create problems due to prolonging use of 193nm lithography. To scale down the feature sizes continually, more complex design rules and multiple patterning are used widely. These changes make automatic generation of physical layout more difficult meet the design rules. We propose a routing algorithm for designing standard cells with 15nm technology based on a double patterning compliant layout template with finer grid pitches. We use Boolean expressions to model a routing problem and solve the model using an SAT solver.
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