Deterministic BIST Using Multiple Polynomial LFSR Reseeding for Low-Power Testing
碩士 === 元智大學 === 資訊工程學系 === 104 === Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition fillin...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90942002025638280770 |