Switching-based Multiple-polynomial LFSR Reseeding for Test Data Compression

• Main Authors: Yan-Jin Liu, 劉彥槿
• Other Authors: Wang-Dauh Tseng
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/45093217537402040401

碩士 === 元智大學 === 資訊工程學系 === 104 === Power consumption and the volume of test data are popular topics in VLSI　Testing field. These are the key factors that will determine the quality of the final data testing results. Built-in self-test (BIST) architecture is a technique which can self-test and verify the data inside the equipment without any other externality, resulting the reduction of test data volume.　　 This thesis which is based on the method of multiple linear feedback shift register architecture, proposes a method to achieve better test compression ratio. The method proposed in this thesis is the use of multiple polynomials and linear feedback shift register to halve the length of the technology and the test data with parity do distinguish and thrown into two equal length linear feedback shift register to generate test data to perform reseeding , test data and two linear feedback shift register generated fused into the final data.Experimental results show that by using the proposed method in ISCAS '89 circuit,we can significantly achieve better compression ratio than similar works.