| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 104 === With the rapid growth of wireless communication systems, the operating frequency of application systems becomes higher gradually. Wireless systems require pure oscillation signal, phase-locked loops （PLLs） may suppress the noise of oscillator and provide better phase noise.
In the thesis, we design a synthesizer adopting a charge-pump PLL for X-band applications. Since the architecture of PLL circuit design is operating in high frequency, we use a LC-tank oscillator to meet specifications. With the characteristic of high Q and high-frequency operation, the LC-tank oscillator is different from the ring oscillator. In order to realize high-speed divider, we adopt current-mode logic to operate at high frequencies and then we can use the traditional logic circuit as the following divided stage.
We use 0.13um 1P5M CMOS technology to realize, simulate and tape out the adopted PLL circuit. The operating frequency for the PLL circuit can reach 7~8 GHz and its power consumption is 15.768 mW at the supply voltage of 1.2V.
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