| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 104 === In this thesis, a digital integrated circuit verification platform is built with the Universal Verification Methodology (UVM). UVM is an abstract framework that provides a number of components to build a verification platform running at Register Transfer Level (RTL), including the device under test, test vectors, and a reference model. The goal of the verification platform is to verify LC-3, which is a 16-bit RISC microprocessor for educational purpose, by functional coverage, and to ensure the RTL code matches the design specifications. Modern integrated circuits are getting much more powerful and complicated and a number of different IPs are integrated in one chip. RTL simulation much is faster than gate-level simulation. The more complete RTL is simulated and verified, the fewer problems would result from the integration of multiple IPs. With fully covered RTL verification, the subsequent verification process at lower levels would run much faster.
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