| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 104 === In recent years, complexity of the circuit design is gradually increased, it take more time to analyze the circuit performance, Whether the design of analog or digital it take long time to analyze the circuit performance and it is very inefficient. If the circuit analysis time can be reduced, circuit designers can obtain the analysis results quickly.
This thesis presents an analysis method to analyze the performance of analog low-pass filter behavioral model based on Verilog-A hardware description language. In this thesis, two analog filter behavioral models are analyzed: Sallen-Key low-pass filter and second-order switched capacitor low-pass filter. Firstly, construct analog behavioral model using Verilog-A, and analyze the performance and simulation time of behavioral model and CMOS circuits. All circuits are implemented using TSMC 0.18μm 1P6M CMOS process technology. From the simulation results, the analysis performance of behavioral model and CMOS circuit are very close. However, the simulation time of behavioral model is much less than that of CMOS circuit.
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