| Summary: | 博士 === 國立臺北科技大學 === 資訊工程系研究所 === 104 === Energy efficiency becomes a critical consideration in computer engineering due to the rise of mobile, battery-powered devices. Nowadays, the modern hardware provides many features for reducing power and energy that require effective software control. Dynamic voltage and frequency scaling (DVFS) is a well-known and efficient technique for reducing power. The central idea of DVFS technique on general-purpose applications is to supply a minimal voltage and frequency when the CPU is in the idle mode. This dissertation proposes different types of DVFS approaches, including: lowest energy regression, decoding video DVFS and scheduling based DVFS, for different type of applications to predict the computing complexity and supply a just-enough voltage and frequency setting.
This dissertation can be divided into three parts: First, the existence of a critical speed and the memory access rate-critical speed equation (MAR-CSE) is proved theoretically and practically. A lowest energy DVFS boundary for Dynamic Voltage and Frequency Scaling is defined. Secondly, a table-based DVFS mechanism for frame decoding is proposed that can effectively reduce the power consumption of a processor by exploiting the frame-decoding complexity features. Finally, a novel scheduling based DVFS approach is proposed that schedules applications to cores in a multi-core system with homogeneous cores.
Taking advantage of all energy-saving opportunities requires the detailed platform, implementation and environmental information. From the experiment results, we reach the exciting conclusion that near-optimal power management is possible on real operating systems, with certain platforms.
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