| Summary: | 碩士 === 國立聯合大學 === 電機工程學系碩士班 === 105 === The purpose of this thesis is to implement a parallel processing on FPGA (Field Programmable Gate Arrays) for the image compression and decompression technique based on differential operation and layered coding. For the color space conversion, differential operation and layered coding in the above image compression technique, the parallel processing will be performed through FPGA. The primary features of the image compression algorithm are less computation and addition/subtraction needed only. In this thesis, we propose two new methods of creating difference table: serial difference table and layer difference table to make great improvement for the speed of layered coding, and the latter contribution is particularly large. Finally, the parallel processing algorithm of both image compression and decompression is implemented on the Altera DE2-115 development board. This system adopts a FPGA as a core and with RS232 transmission interface, and the images can be transferred between computer and DE2 board. The experimental result show that parallel processing algorithm does enhances the speed of image compression up to 40% and decompression up to 60%.
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