| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 104 === For dynamic random access memory (DRAM), data retention time of DRAM cells dominate the refresh power consumption and fabrication yield. Although extending the standard refresh period is one of the most widely used method for reducing refresh power, however, it will inevitably cause further data retention faults. Recently, there are many techniques proposed for repairing or avoidance of these faults. For example, error detection and correction codes (EDAC) can be used to correct data retention faults. However, EDAC requires extra hardware cost for implementing the encoding/decoding circuits. Besides, it also sacrifices the protection ability for transient faults. Other techniques try to logically partition the DRAM address space into spatially disjoint regions. Thereafter, a suitable refresh period is allocated for each region. The main drawback is that the refresh period is limited by the cell with the shortest data retention time in each region.
In this thesis, two adaptive block-based refresh techniques for reducing DRAM refresh power and mitigation of data retention faults are proposed. For the first technique, we develop a control word remapping approach. We partition a memory bank into spatially disjoint sub-banks. A sub-bank can recover a row which includes data retention faults. We remap this row to the bottom of this sub-bank by the associated control word and allocate a suitable refresh period for it. Alternately, the other rows in the same sub-bank can use an extended refresh period. The second technique is an address remapping approach. We define a cluster region formed by remapping the rows which include data retention faults. We reconfigure the mapping between the physical address and logical address to achieve this goal. Then, we provide the required refresh periods for these rows to mitigate their faults. Thereafter, the rows which do not belong to the cluster region can use an extended refresh period. These two techniques reduce the number of rows which should be refreshed too often. Besides, the rows which contain data retention faults still can be refreshed adequately.
Experimental results show that sub-bank address remapping technique can save 74.97% refresh power and CAM-based address remapping technique also can save 86.67% refresh power with less than 1% hardware overhead for a 1-Gb DRAM. In our simulation, we assume that the data retention time follows the normal distribution. If we decrease the standard refresh period from 64 ms to 32 ms, 16 ms, and 8 ms; the yield can be improved 0.68, 0.96, and 1.09 times, respectively.
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