High-Accuracy Instrumentation Amplifier Design with Gradient Cancellation Layout Technique

• Main Authors: Pranata Wibawa Sanjaya, 葉成林
• Other Authors: Poki-Chen
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/c6zaa3

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === This thesis provides the completion of layout technique utilizing devices placement in a special pattern to generate high-order of gradient error mismatch cancellation capability. The methodology presented in this thesis is an easily understandable mean of creating layout patterns in order to be used for any quantity and variety of devices, and any order of gradient error mismatch as required by the designer. Moreover, multiple layout patterns are available for layout engineers depending on the condition and size of the device. This proposed methodology has been rigorously tested through calculation and MATLAB simulation. The chip fabrication measurement has also shown successful results. Even though these chips are packaged by two different companies, all the measured chips continue to show that higher order pattern achieves better accuracy. An instrumentation amplifier design also has been made to implement the proposed methodology in order to achieve high order accuracy among the critical devices. It utilizes resistive feedback topology with balancing technique for its resistors. The design is implemented using TSMC 0.18 m standard process. Based on post-simulation, it has 2% gain error with 2.3MHz Bandwidth, 0.88mV offset voltage, 58dB CMRR and 106dB PSRR. The total chip area is 0.129mm2 with ±1.5V supply voltage 611A current consumption.