The VLSI Architecture of a High-Throughput Configurable Pre-processor for MIMO Detections

• Main Authors: Tzu-Ting Tseng, 曾梓庭
• Other Authors: Chung-An Shen
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/94532926801103773887

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === This thesis presents the VLSI architecture and circuit implementation of a high-throughput configurable pre-processor for 4×4 Multiple-Input Multiple-Output (MIMO) systems. The proposed configurable pre-processor can support three functions – QR decomposition (QRD), Sorted QRD (SQRD) and Minimum Mean Squared Error SQRD (MMSE-SQRD) by sharing the Process Unit (PU) and transferring the data stream. Furthermore, in order to achieve the goal of high throughput, the proposed design is architected in a pipelined systolic array structure. The proposed configurable architecture provides a choice of a trade-off between the Bit Error Rate (BER) performance and power consumption in MIMO detector processing. Moreover, the channel matrix is operating in two-stage processor: complex-value Givens rotation and real-value Givens rotation in order to reduce the hardware complexity by reducing the computational complexity. Specifically, we proposed a novel norm calculation strategy such that large parts of the norm calculation operators can be reduced. The proposed pre-processor implemented in TSMC 90nm CMOS technology achieves the throughput up to 55 mega per second for decomposing 4×4 channel matrix, and outperforms the related works with equal functionality and architecture.