| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === In the RF transceiver, PLL are very important, PLL characteristics include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider. This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).
First, a wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The die area is 0.859 × 0.817 mm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 5.26 mW and the locking range is from 6.2 to 12.6 GHz (68.09%) at injection power Pinj = 0 dBm.
Secondly, a wide locking range divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a capacitive cross-coupled nMOS pair and two shunt 4th-order RLC resonators. At the drain-source bias of 0.75 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-2 ILFD is 7.5 GHz (102.04%) from 3.6 to 11.1 GHz, the ILFD has overlapped locking ranges. The core power consumption is 4.875 mW. The die area is 1.008 × 1.182 mm2.
Finally, a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-4 ILFD uses a capacitive cross-coupled nMOS pair and two shunt 4th-order RLC resonators. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm, the locking range of the divide-by-4 ILFD is 6 GHz, from the incident frequency 13 to 19 GHz and the locking range percentage is 37.5%. The die area is 1.008 × 1.182 mm2. The power consumption of ILFD core is 7.09 mW.
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