A 1/2.5-Rate Clock and Data Recovery Circuit for 100Gb/s Ethernet in 40 nm Technology

• Main Authors: Chia-Kai Cheng, 鄭家凱
• Other Authors: Tai-Cheng Lee
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/42045406149607511904

碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === In June, 2010, IEEE P802.3ba is generated officially. It defines the specification of 40GbE and 100GbE. The purpose is to extend the operation speed of the IEEE 802.3 agreement to 40Gbps and 100Gbps, and at the same time it also accords the current agreement and the demand of the transmission distance. At the definition of IEEE P802.3ba, the 100GbE is used four channels of 25Gbps output of with wavelength division multiplexing to achieve the purpose of high speed transmission. At optical communication systems, since the cost of the transmission line channel is very expensive, in order to reduce the cost, we usually hope we can transmit higher frequency data in single channel. At the 100GbE receiver system, we need to deserialize four channel 25Gbps signal into ten channel 10Gbps. Unlike the conventional power of 2 deserializer, the 2:5 data ratio would suffer from more complicate design, and consume more area and have more power dissipation. A 1/2.5-rate clock and data recovery (CDR) circuit is proposed in this thesis. We can deserialize the signal without 2:5 deserializer to reduce the hardware resource. This CDR is implemented in TSMC 40nm CMOS technology. At 1V power supply, it only consumes 51.5mW/Channel.