An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration
碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data trans...
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2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29974491710040039724 |
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ndltd-TW-104NTU054280822017-06-03T04:42:00Z http://ndltd.ncl.edu.tw/handle/29974491710040039724 An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration 具有校正頻寬之全數位資料回復電路 Yu-Syuan Du 杜昱璇 碩士 國立臺灣大學 電子工程學研究所 104 This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7. Shen-Iuan Liu 劉深淵 2016 學位論文 ; thesis 42 en_US |
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en_US |
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Others
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7.
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| author2 |
Shen-Iuan Liu |
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Shen-Iuan Liu Yu-Syuan Du 杜昱璇 |
| author |
Yu-Syuan Du 杜昱璇 |
| spellingShingle |
Yu-Syuan Du 杜昱璇 An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| author_sort |
Yu-Syuan Du |
| title |
An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| title_short |
An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| title_full |
An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| title_fullStr |
An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| title_full_unstemmed |
An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
| title_sort |
all-digital clock and data recovery circuit with bandwidth calibration |
| publishDate |
2016 |
| url |
http://ndltd.ncl.edu.tw/handle/29974491710040039724 |
| work_keys_str_mv |
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