An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration
碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data trans...
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| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29974491710040039724 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7.
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