DFT and ATPG of Two-pattern Tests for Dual-rail Asynchronous Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This thesis presents a two-pattern test methodology for dual-rail asynchronous circuits. Our design for testability (DFT) is based on a full-scan, clock-less, Dua...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50753556141892622725 |