A Mixed-Mode DLL and an All-Digital DLL in Wide-Range, and a HomePlug AV2 PLC Transceiver

• Main Authors: Min-Han Hsieh, 謝旻翰
• Other Authors: Chung-Ping Chen
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/93807234833724400580

博士 === 國立臺灣大學 === 電子工程學研究所 === 104 === While the big data generation coming, with the demands of the data communications, a high-speed and robust communication system has become very important. In this thesis, not only a mixed-mode multi-phase distributed delay-locked loop (DDLL) and an all-digital low-power low-cost delay-locked loop (DLL) have been proposed, but also a digital front-end and an analog front-end for HomePlug AV2 high-speed powerline communication (PLC) system has been presented. In the mixed-mode multi-phase DDLL, the phase insertion technique was adopted to achieve wide operating frequencies. The proposed architecture achieves wide operating frequency range by adding a digital phase selector into the DDLL as a coarse-tune block and a automatic frequency detector. The digital phase selector outputs the selected phases according to the detected operating frequency with the most delay for the following tunable delay cells. Thus the selected phases will be fin-tuned by the tunable delay cells for minimizing the phase errors independently. The DDLL was fabricated in 90 nm CMOS technology and occupies 0.0644 mm2 active areas. The operating frequency range is from 2 GHz to 8 GHz, with 1.93 ps and 1.53 ps phase error, respectively. An all-digital DLL (ADDLL) with a phase-tracing delay unit (PTDU) is the second proposed DLL in the thesis to achieve wide operating frequency range, low power and low cost. For the wide-range DLL, the long delay line is replaced by a phase-tracing delay unit (PTDU) which includes two gated ring oscillators (GROs) for generating the wide delay range with a reduced die area. According to the dual loop control scheme in this work, the input clock rising edge and falling edge are tracked independently to ensure that the ADDLL output maintains the duty cycle of the input reference. Furthermore, the ADDLL utilizes an open-loop scheme to achieve fast lock time of 5 clock cycles for all supported input frequencies. The proposed ADDLL has been fabricated in TSMC 90 nm CMOS technology and supports a wide operating frequency range from 6.7 MHz to 1.24 GHz within a small active area of 0.0318 mm2. The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz and achieves the FOM of 0.206. A SoC transceiver for the broadband powerline communication system in HomePlug AV2 standard is presented in this thesis. The transceiver consists of a 10-bit 180 MS/s current steering DAC and a line driver with 86 MHz bandwidth, a PGA with a bandwidth in 86 MHz, a 10-bit 180 MS/s pipelined ADC in receiver, and a PLL. In HomePlug AV2, the proposed transceiver achieves 36 dB multi-tone power ratio (MTPR) in the transmitter and 16 dB loopback MTPR in the receiver under 64–QAM constellation map with -23 dB average error vector magnitude (EVM) in 461 Mbps data rate. The transceiver was fabricated in TSMC 90 nm technology and occupies 2.7 mm2 active area. In HomePlug AV2, the transceiver consumes 30 mW, 1.1 W, 25 mW and 16 mW power in DAC, line driver, ADC and PGA.