FPGA-Based Signal Processing And Control System For Digital Positron Emission Tomography

碩士 === 國立臺灣海洋大學 === 電機工程學系 === 104 ===   The main objective of this research is to design and implement the signal processing and control system of digital positron emission tomography. Two traditional discrimination methods for ray Depth of Interaction (DOI) determination have been implemented in d...

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Bibliographic Details
Main Authors: Lee, Chun-Wei, 李俊緯
Other Authors: Wu, Tzong-Dar
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/98483109492634560616
Description
Summary:碩士 === 國立臺灣海洋大學 === 電機工程學系 === 104 ===   The main objective of this research is to design and implement the signal processing and control system of digital positron emission tomography. Two traditional discrimination methods for ray Depth of Interaction (DOI) determination have been implemented in digital scheme and their performances were analyzed and compared.   The signal processing system consists of digital pulse capturing module, position estimation module, energy calculating module and scintillator discrimination module for DOI estimation. The control system consists of time coincidence and data formatting module, data combining module, and data transformation module. The whole system is designed and implemented on DE3 field-programmable gate array (FPGA) platform developed by Terasic Company, in which the Verilog hardware description language (HDL) is used for FPGA programming.   In DOI determination, we analysised and compared two Pulse Shape Discrimination (PSD) methods for LYSO and LSO scintillators in phoswich assemblies, which are Rise Time Discrimination (RTD) and Delayed Charge Integration (DCI). According to the simulation and hardware experiment results, it is clear that DCI method has better performance than the RTD method.   After the integration of the signal processing system and the control system, the system testing results show that the input signal hold time, dead time, and delay time of the whole digital system are 20 ns, 1.18 μs, and 1.34 μs, respectively.