Design of 5GHz Low Power RF Receiver Font-end Circuits

碩士 === 國立臺灣海洋大學 === 電機工程學系 === 104 === In this thesis, we design 5GHz low power RF receiver font-end circuits, which consist of a voltage-controlled oscillator (VCO), a low noise amplifier (LNA) and a mixer. The circuits are simulated with the Agilent Advanced Design System (ADS) software supported...

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Bibliographic Details
Main Authors: Chi, Yu-Ting, 紀宇廷
Other Authors: Yeh, Mei-Ling
Format: Others
Language:zh-TW
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/73141946211680218275
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Summary:碩士 === 國立臺灣海洋大學 === 電機工程學系 === 104 === In this thesis, we design 5GHz low power RF receiver font-end circuits, which consist of a voltage-controlled oscillator (VCO), a low noise amplifier (LNA) and a mixer. The circuits are simulated with the Agilent Advanced Design System (ADS) software supported by National Chip Implementation Center (CIC), and circuit components use the TSMC 0.18 um 1P6M CMOS Mixed-Signal models. The first chip is a voltage-controlled oscillator (VCO) which uses the complementary architecture as the main feature to combine the advantages of NMOS and PMOS. The circuit uses LC tank and CMOS structure to achieve low power and decrease the wafer area. The measurement results show that the tuning range is 600MHz, the phase noise is -111.2 dBc/Hz at 1MHz offset from the carrier frequency of 4.6 GHz. The FOM can achieve -181.7 dBc/Hz, the power consumption is 2.15mW, and the chip area is 0.852*0.65 mm2. The second chip is a low noise amplifier (LNA) which adopts cascode architecture and current mirror to achieve the low power. The measurement results show that the maximum power gain (S21) is 8.75 dB. The input reflection coefficient S11 and output reflection coefficient S22 are lower than -13 dB and -9 dB, respectively. The minimum noise figure is 5.8 dB from the carrier frequency of 5 GHz. The P1dB and input third-order intercept point (IIP3) are -20dBm and -15dBm. The power consumption is 4.2mW at 1V supply voltage. This LNA occupies an area of 1.5*1.0 mm2. The third chip is a mixer with the single-balanced architecture. In the transconductance stage, we add two transistors operating between the saturation and linear region which are equivalent to a resistor to improve the linearity. In noise part, we use noise cancellation technique to reduce the noise. The simulation results show that the conversion gain is 8.4dB, the noise figure is 25dB, the P1dB is -16dBm, the IIP3 is -10dBm from the carrier frequency of 5 GHz. The power consumption is 8mW at 1V supply voltage, and the chip area is 1.3*0.75 mm2.