| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 104 === Memories have been considered as one of the major drivers of CMOS technology, due to their high density, high capacity, critical timing, sensitivity, etc. Memory diagnosis is therefore important for technology and product development. Memory failure pattern identification is traditionally an essential task for diagnosis. As memory density and capacity continue to grow, the amount of test data also keeps increasing, thus a more efficient failure pattern extraction method is required. In this thesis, we propose a sweep-line-based memory failure pattern extractor to speed up the extraction process. The proposed tool can extract memory failure patterns from an industrial case of 20 state-of-the-art wafers in about 35 minutes, reducing 15% analysis time as compared with the sparse-matrix-based method that is the best so far. In our experiments of the industrial case, we are also able to identify a critical failure pattern that was not defined before, showing its more robust pattern identification capability.
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